Complex SOC on 90 nm and lower processes generate new fault models. New complex SOC devices using 90 nm and lower processes exhibit more than simple stuck-at fault models. AC Scan patterns are being deployed in both engineering and production for at-speed go/no-go testing. However, identifying the source of speed related problems continues to be a challenge for engineers. The problem being solved in this invention is how to efficiently compress and accumulate massive amounts of failure data from multiple runs of test patterns on die on these larger number of wafers or packaged devices. By analyzing and organizing the raw data according to the method of this invention it becomes economically efficient and physically possible to display the useful information.
Scan Basics
To explain the new software process, it is first necessary to provide some background on established techniques of SCAN and AC-SCAN in semiconductor test. The approach of scan methodology is to replace all flip-flops in a design with scan flip-flops. Scan flip-flops provide two paths into each flip-flop: one for the mission of the design, and a second to facilitate test.
Scan Flip-Flops
There are two most common methods of implementation today:                MUXD                    This scan flip-flop approach places a mux on the front end of the D-input. The selector to the mux, known as the scan enable, determines whether to use the mission mode input or the scan test input.                        LSSD                    Another common scan flip-flop approach is to use two clocks. One clock latches the mission path input into the flip-flop while the second clock latches the scan test input data into the flip-flop.Scan Chains                        
By stitching all of the scan flip-flops, or scan cells, together into one or more scan chains, each flip-flop can get preset or observed. This allows for test patterns to be constructed that will concentrate on finding faults in mini sub-circuits.
See the circuit example shown in FIGS. 1 and 2. The first illustration shows the circuit prior to scan insertion, and the second shows the circuit after a MUXD scan insertion. In FIG. 2, Logic Circuit After Scan Insertion, notice that each flip-flop has two input paths as controlled by a multiplexor on the input. When the scan enable “SE” is asserted, the scan chain operates as a shift register. This allows for each flip-flop to be set to a specific state. It also allows for the observation of each flip-flop state as the values are shifted out of the device onto the scan output “SO”. We have numbered each flip-flop, or scan cell, for the purpose of referencing.
For this example, the ‘and’ gate can be tested by shifting data into scan cells 3 and 2. After the desired test condition has been loaded, the scan enable is de-asserted and a clock can be applied to capture the output of the combinational logic as observed at scan cell 1. The scan enable is once more applied and the result data as captured at scan cell 1 can be shifted through the scan chain until it can be seen on the device output for the scan chain.
AC-Scan
The principles of ac-scan are very similar to that of scan. The major difference is that the clock that captures the output of the combinational logic into the observation scan cell is timed to the clock that placed the test condition at the input of the combinational logic. For example, if the spacing between the assertions of the two clocks is 1 ns, the test frequency is 1 GHz.
In the following timing diagram FIG. 3, note that the scan enable “SE” is asserted and four bits of data are loaded into the scan chain through the scan input “SI”. Each bit must be clocked “CLK” however, the last of the four clocks is retimed to allow controllable proximity to the capture clock which is applied after scan enable is de-asserted. Now that the tested state is captured in the observation flip-flops, the values can be shifted out on the scan output “SO”. This “Load-Capture-Unload” operation is known as a “Scan Pattern” and may be performed thousands of times throughout a test pattern set.
From the example circuit in FIG. 2, there are only 7 paths through the 3 gates as listed:                1. From scan cell 3 through the inverter into scan cell 2        2. From scan cell 3 through the ‘and’ gate into scan cell 1        3. From scan cell 2 through the ‘and’ gate into scan cell 1        4. From scan cell 3 through the ‘and’ gate, through the ‘or’ gate, into scan cell 0        5. From scan cell 2 through the ‘and’ gate, through the ‘or’ gate, into scan cell 0        6. From scan cell 1 through the ‘or’ gate into scan cell 0        
Test patterns can be generated to check the speed of each of these paths for this design. However, with the magnitude of typical designs today, it is impossible to test all paths individually.
There are multiple clocking approaches deployed today including “Launch on Last Shift” and “Launch on Capture” (also known as 2-Cycle Capture) techniques using both external clocks driven by the tester and internal clocks from a PLL inside the device. However, in all approaches, the basic concept of one clock to apply the input to the logic under test and another clock to latch the results into scan cells remains the same. The proximity of these two clocks determines the frequency that the logic is tested at. The proximity of the two clocks is the variable which is swept through a range. Each setting of the two clocks is a testpoint and is referred to as an increment. The proximity may start out wide to enable many passes and with each increment get smaller until no passes are recorded or the proximity may start out very narrow with few passes and progressively widen.
Functional Tester Background
Historically, testers apply a set of simulated stimulus, and validate that the response on the device outputs match the results expected from the simulation. Functional testers are designed to report in a go/no-go fashion that all of the outputs matched the expected results for all checked strobe points or not. Functional testers are not architected to understand design criteria of the device under test such as the scan structures. Thus, while testers can understand which output signals contained failures, each output signal can represent tens of thousands of internal scan cells.
Thus it can be appreciated that what is needed is:
a method to associate fail data measured on a tester with the structural, logical, and physical context and performance metric enabling a rapid analysis and understanding of possible clusters of failure that stem from a common design or manufacturing origin; a way to select from huge volumes of test data the information to analyze patterns in defects that result in failures at or above certain speeds of operation; a way to view failures in different contextual backgrounds to determine commonality among failures that may reveal a addressable cause; a way to compress data without losing essential details for analysis in a reasonable and economic time; a way to present data for analysis that can be more easily understood and communicated; and a method of tracing the envelope of failures as a test parameter is swept through a range of values.